1. Field of the Invention
The present invention relates to a clocking scheme for the transfer of data between two or more electronic devices.
2. Description of Related Art
Data is typically transferred between two electronic components in accordance with a predefined clocking scheme. For example, transferring data from a memory device to a processor typically includes, among other things, the steps of generating a data request signal that is sent from the processor to memory and then sending the requested data from memory to the processor. Both the data request signal and the data are typically latched into the respective devices with clock pulses from a system clock. Consequently, it takes at least two clock cycles of the system clock to transfer data from one device to another device.
It is desirable to provide a bus that has a high data rate, so that the bus does not slow down the speed of the system. One way to increase the data rate is to enlarge the size of the bus. Providing a larger bus, increases the number of pins of the devices and the overall size of the system. High data transfer rates can also be achieved by increasing the speed of the clock. Increasing the clock frequency may create timing problems, particularly if the clock is routed to multiple components. It would therefore be desirable to have a data transfer clocking scheme that would increase the data rate of a system without increasing the width of the bus or the speed of the clock.